The present invention generally relates to simulation methods and computer-readable storage media, and more particularly to a simulation method for carrying out a layout analysis and the like of a semiconductor integrated circuit, and to a computer-readable storage medium which stores a program for causing a computer to carry out procedures of such a simulation method.
Recently, the integration density of semiconductor integrated circuits, namely, Large Scale Integrated circuits (LSI), has increased considerably. As a result, the performance of the circuits is greatly affected by layout patterns and layout positions of cells and circuits formed by such cells, and inconsistencies introduced during production of the circuits. In addition, it becoming more difficult in circuit simulation to sufficiently represent circuit characteristics, such as characteristics of the cells. For example, even when the cells or the circuits have the same shape, the circuit characteristics may differ depending on the layout positions and the layout shapes. The circuit characteristics of the cells or circuits having the same shape become different depending on the layout positions and the layout shapes of the circuit mainly due to deviation of the circuit characteristics depending on the pitch of polysilicon gates of transistors and deviation of the circuit characteristics depending on stress caused by Shallow Trench Isolation (STI). Such deviations of the circuit characteristics are becoming more conspicuous with the increasing integration density of the LSIs. In addition, the effects of the layout patterns and the layout positions of the cells and the circuits and the inconsistencies introduced during production of the circuits on the circuit characteristics are becoming more and more complex.
Moreover, before and after assembly of the LSIs, the package stress becomes different depending on the positions of the cells and the circuits. Accordingly, it may be expected that the circuit characteristics will similarly differ before and after assembly of the LSIs.
Furthermore, the effects of not only the characteristics of the elements such as the transistors, but also wirings or interconnections connecting the elements and the circuits are becoming more conspicuous. Consequently, even in the case of identical circuits or identical cells, the circuit characteristics will differ depending on the wirings in the periphery of the identical circuits or identical cells.
There are demands to take the above described phenomena into consideration when carrying out a simulation, in order to improve the accuracy with which the circuit characteristics are predicted (hereinafter referred to as the prediction accuracy of the circuit characteristics).
A technique which analyzes a peripheral state of an target element or circuit, and feeds back an analysis result to a simulation environment is known.
FIG. 1 is a flow chart for explaining an example of a related simulation method. In FIG. 1, a step S1 carries out a layout analysis based on layout data, which indicate layout patterns and layout positions of elements and circuits. A step S2 makes a modification based on a result of the layout analysis, with respect to a net list of characteristics of cells that is, cell characteristics forming the circuit, which is being extracted or is already extracted. A step S3 reextracts the cell characteristics from the modified net list. A step S4 analyzes the reextracted net list. The steps S1 through S3 are repeated every time a modification is applied to the layout.
Normally, analysis in the semiconductor chip level, such as a timing analysis, is carried out using the cell characteristics, and no simulation is carried out with respect to the characteristic of the cell itself.
According to the techniques described above, a modification is made based on the result of the layout analysis, with respect to the net list or circuit information of cell characteristics forming the circuit, which is being extracted or is already extracted. For this reason, it is necessary to reextract the cell characteristics from the modified net list. In addition, even for identical cells, it is necessary to extract the cell characteristics for every layout state.
Therefore, because the net list is modified when modifying the layout, it is necessary to extract the cell characteristics from the net list every time the layout modification is made or, for every layout. As a result, it is difficult to efficiently carry out the simulation and to improve the prediction accuracy of the circuit characteristics.